In recent years, so called a Fin type MISFET has been proposed as one type of MIS type field effect transistors (hereinafter referred to as “MISFET”). The Fin type MISFET has a rectangular parallelepiped semiconductor raised portion, and a gate electrode is provided so as to extend over the rectangular parallelepiped semiconductor raised portion from one side face across the top face to the opposite side face of the semiconductor raised portion. A gate insulating film exists between the rectangular parallelepiped semiconductor raised portion and the gate electrode, and a channel is formed principally along the opposite side faces of the rectangular parallelepiped semiconductor raised portion. It is known that such a Fin type MISFET is advantageous for miniaturization because the channel width can be situated along a direction vertical to a substrate plane, and in addition, the Fin type MISFET is advantageous for various characteristic improvements such as improvement of a cutoff characteristic and a carrier mobility and reduction of short channel effects and punch through.
As such a Fin type MISFET, Japanese Patent Laid-Open No. 64-8670 (Patent Document 1) discloses a MOS field effect transistor (MOSFET) characterized in that a semiconductor raised portion having a source region, a drain region and a channel region has a shape of rectangular parallelepiped having side faces almost vertical to the plane of a wafer substrate, the rectangular parallelepiped raised portion has a height that is larger than the width, and a gate electrode extends along a direction vertical to the plane of the wafer substrate.
The patent document describes as an example a configuration in which a part of the rectangular parallelepiped raised portion is a part of a silicon wafer substrate and a configuration in which a part of the rectangular parallelepiped raised portion is a part of a monocrystalline silicon layer of a SOI (Silicon on insulator) substrate. The former is shown in FIG. 1(a) and the latter is shown in FIG. 1(b).
In the configuration shown in FIG. 1(a), a part of a silicon wafer substrate 101 is a rectangular parallelepiped portion 103, and a gate electrode 105 extends from one side to the other across the top of the rectangular parallelepiped portion 103. In the rectangular parallelepiped portion 103, a source region and a drain region are formed on opposite sides of the gate electrode, respectively, and a channel is formed under an insulating film 104 below the gate electrode. The channel width is two times as large as the height (h) of the rectangular parallelepiped portion 103, and the gate length is equivalent to the width (L) of the gate electrode 105. The silicon wafer substrate 101 is anisotropically etched to form a trench, and the rectangular parallelepiped portion 103 is formed of areas left on the inner side of the trench. The gate electrode 105 is provided on the insulating film 102 formed in the trench such that the gate electrode 105 extends over the rectangular parallelepiped portion 103.
In the configuration shown in FIG. 1(b), a SOI substrate consisting of a silicon wafer substrate 111, an insulating layer 112 and a silicon monocrystalline layer is prepared, the silicon monocrystalline layer is patterned into a rectangular parallelepiped portion 113, and a gate electrode 115 is provided on an exposed insulating layer 112 so as to extend over the rectangular parallelepiped portion 113. In the rectangular parallelepiped portion 113, a source region and a drain region are formed on both sides of the gate electrode, respectively, and a channel is formed under an insulating film 114 below the gate electrode. The channel width is equivalent to a sum of double the height (a) of the rectangular parallelepiped portion 113 and the width (b) thereof, and the gate length is equivalent to the width (L) of the gate electrode 115.
Japanese Patent Laid-Open No. 2002-118255 (Patent Document 2) discloses a Fin type MOSFET having a plurality of rectangular parallelepiped semiconductor raised portions (raised semiconductor layers 213) as is shown in, for example, FIGS. 2(a) to 2(c). FIG. 2(b) is a cross-sectional view taken along the B-B line in FIG. 2(a), and FIG. 2(c) is a cross-sectional view taken along the C-C line in FIG. 2(a). The Fin type MOSFET has a plurality of raised semiconductor layers 213, these raised semiconductor layers are arranged mutually in parallel, and a gate electrode 216 is provided so as to extend over the central parts of these raised semiconductor layers. The gate electrode 216 is formed along the side faces of the raised semiconductor layers 213 from the top face of the insulating film 214. An insulating film 218 exists between each raised semiconductor layer and the gate electrode, and a channel 215 is formed on the raised semiconductor layer below the gate electrode. Source and drain regions 217 are formed on each raised semiconductor layer, and high-concentration impurity layers (punch through stopper layers) are provided on regions 212 below the source and drain regions 217. Upper interconnects 229 and 330 are provided on an interlayer insulating film 226, and the upper interconnects are connected to the source and drain regions 207 and the gate electrode 216 by contact plugs 228, respectively. The patent document describes that according to the structure described above, the side face of the raised semiconductor layer can be used as the channel width, and therefore the planar area can be reduced as compared to a conventional planar type MOSFET.
If miniaturization and densification are pursued in a semiconductor device comprising a Fin type MISFET, the following problem related to connection (contact) between a source/drain region and a plug will arise.
When a contact is formed on the source/drain region of the rectangular parallelepiped semiconductor raised portion as shown in FIGS. 2(a) to 2(c), the contact area decreases as the width of the semiconductor raised portion (in the width direction in the figure) is narrowed with size reduction, so that sufficient conduction is hard to be obtained. This problem becomes more noticeable as the height of the semiconductor raised portion is increased for obtaining a large current drive force. Alignment of the semiconductor raised portion in the width direction is difficult during formation of contact holes, and connection failures resulting from misregistration tend to occur.
As shown in FIGS. 1(a) and 1(b), wide pad portions can be provided at opposite ends of the semiconductor raised portion, and contacts can be formed in the pad portions, but densification is deteriorated in proportion to the area occupied by the pad portions. It is difficult to uniform the width of the semiconductor raised portion (the width expands near the pad portion) due to influences of the pad portion when lithography or etching is performed.